ECE 445 –Introduction to VLSI Design

Spring 2019, University of Idaho

Lecture notes are here and course handouts are available here.

Homework assignments, project information, and due dates are located here. Homework solutions may not be provided (use grader comments instead).  In case they are provided, they will be posted on BBlearn.

Grades will be posted on the BBLearn site for the course.

Cadence Wiki with FAQs is here, and the tutorials are here.

 

Piazza discussion forum is available here.

 

 

Instructor       : Dr. Vishal Saxena

Email              : vsaxena AT uidaho.edu

Time               : MW 8:00 AM - 9:20 AM

Course dates  : Jan 9 – May 3, 2019

Location         : JEB 021

Office Hours  : MW 11:30AM-12:30PM, or by appointment, at BEL 318.

Holidays         : MLK Day (Jan 21), Presidents’ Day (Feb 18) and Spring Recess (Mar 11-14).

Final Exam time: Thursday, May 9, 8:00 AM – 10:00 AM

Course TA     :  None. Submit HWs to the instructor as directed.

 

Textbooks:  

·          CMOS Circuit Design, Layout and Simulation – R. J. Baker, 3rd Edition, Wiley-IEEE, 2010.

·          CMOS VLSI Design: A Circuits and Systems Perspective, N. Weste and D. Harris, 4th Ed., Addison-Wesley, 2010.

 

Course content (Syllabus)

CMOS transistor models, advanced current mirrors and biasing, review of amplifiers. Opamps: frequency compensation, negative feedback and stability, half circuit analysis.  Voltage references (bandgap reference) and regulators. Fully-differential Opamp design and simulation. Noise, mismatch, and distortion in analog circuits. Analog layout considerations.

 

Prerequisites – ECE 310, or an equivalent course.  

 

CAD software information:

The course will require extensive use of Cadence Design System Tools in Linux environment. Design projects will involve schematic, simulation and layout using a realistic process development kit (PDK).

 

For the design/fabrication of chips in this class, On Semiconductor 0.5µm (C5 with two polysilicon layers and 3 levels of metal) will be used with a MOSIS technology code of SCN3ME_SUBM with a lambda of 0.3µm. Refer to the wiki for information on design rules and process test results and corner parameters.

 

Piazza Discussion Site

We will be using Piazza for class discussion. The course Piazza page is located at https://piazza.com/uidaho/spring2019/ece445 where you can sign up.

The system is highly catered to getting you help fast and efficiently from classmates, TA, and myself. Rather than emailing questions to the instructor, I encourage you to post your questions on Piazza.

 

Workload (Grading) 

25% Homeworks

25% Midterm Exam 1

25% Midterm Exam 2

25% Final Exam

 

 

Course Policies: 

See course syllabus for detailed policies.

 

 

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